Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET) coupled to a capacitor cell. Programmable address decode circuits and buffers are needed in conjunction with the DRAM array to allow faulty rows and/or columns in a memory array to be replaced by functional redundant rows and/or columns. An example of a redundancy repair scheme is shown in U.S. Pat. No. 5,324,681 issued Lowrey on Jun. 28, 1994. Another is provided in U.S. Pat. No. 4,051,354 issued Choate on Sep. 27, 1997. Another is provide in U.S. Pat. No. 5,327,380 issued Kersh III on Jul. 5, 1994.
With the increasing array density of successive generations of DRAM chips, the attractiveness of merging other functions onto the chip, e.g. programmable address decode logic, also increases. However, any successful merged technology product must be cost competitive with the existing alternative of combining separate chips at the card or package level, each being produced with independently optimized technologies. Any significant addition of process steps to an existing DRAM technology in order to provide added functions such as high speed logic, SRAM or EEPROM becomes rapidly cost prohibitive due to the added process complexity cost and decreased yield. Thus, there is a need for a means of providing additional functions on a DRAM chip with little or no modification of the DRAM optimized process flow.
Programmable address decode circuits conventionally employ one time programmable switches in such decode circuits. Fuses and antifuses, present in circuits peripheral to the DRAM chips, are one method for constructing address decode logic. The fuse or antifuse integrally combines the functions of a switching element which makes the interconnection and a programming element which stores the state of the switching element, either “off” or “on,” e.g. a blown or unblown fuse. A fuse or antifuse, however, has the disadvantage of not being reprogrammable. This single-time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required. The fuse or antifuse further has the disadvantage on not being fabricated according to the DRAM process flow.
Micron Technology, Inc. taught in U.S. Pat. No. 5,324,681 which issued to Lowrey et al. on Jun. 28, 1994, that one time programmable (OTP) memory cells formed as MOSFETs could be used to replace laser/fuse programmable memory cells for applications such as OTP repair of DRAMs using redundant rows and columns of DRAM memory cells and OTP selection of options on a DRAM (such as fast page mode (FPM) or extended data out (EDO)). One of the key advantages of that capability is the ability to program the OTP memory cells after the DRAM memory chip is packaged (a decided advantage over previous solutions). However, the invention in the Lowrey patent still has the disadvantage of single-time programmability.
Another approach to solving the programmable switching problem is described in U.S. Pat. No. 5,764,096, which issued to Lipp et al. on Jun. 9, 1998. U.S. Pat. No. 5,764,096 provides a general purpose non-volatile, reprogrammable switch, but does not achieve the same using the commonality in basic DRAM cell structure. Thus, the Lipp patent does not achieve the desired result of providing non-volatile memory functions on a DRAM chip with little or no modification of the DRAM process flow.
Still another alternative to programmable interconnects, e.g. logic switching circuits, uses a metal oxide semiconductor field effect transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based field programmable gate arrays (FPGAs) are reprogrammable and use a DRAM process flow, but have a disadvantage in that the programming of the switching elements is lost whenever power is turned off. A separate, non-volatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up. This need again increases the fabrication complexity and requires significant additional chip surface space.
Thus, there is a need for DRAM technology compatible non-volatile memory cells which can be used as programmable logic arrays (PLAs). It is desirable that such DRAM technology non-volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such DRAM technology non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.